[ESL Modelling] SystemC

SystemC is a free library for hardware modeling using C++. Initially promoted by the Open SystemC Initiative (OSCI), it is now maintained by Accellera and designated as the IEEE-1666 standard. Each hardware component in SystemC is defined using C++ classes, which can contain subcomponents, supporting both Transaction Level Modeling (TLM) and net-level modeling. SystemC can be used for both simulation and synthesis, and it was originally designed as an RTL-equivalent method to express digital logic within C++.

Key Elements of the SystemC Core Library:

• Module System and Inter-Module Channels: C++ class instances are hierarchically instantiated according to the circuit component structure, similar to how RTL modules are instantiated with each other.
• User-Space Kernel: This kernel provides system time, simulation pauses, and name resolution functions. It implements an Event-Driven Simulation (EDS) event queue that loosely follows the semantics of VHDL, offering event notifications and threads. These threads are non-preemptive, allowing lightweight approaches to data structure locking. However, running SystemC on multi-core workstations can present challenges.
• Compute/Commit Signal Paradigm: This paradigm is essential for avoiding shoot-through in zero-delay clock domains, a condition where one flip-flop changes output before another reads the previous value.
• Arbitrary Fixed-Point Integer Library: Since hardware employs buses and counters of varying widths, SystemC provides corresponding signed and unsigned variables with different bit-widths.
• Waveform Output: SystemC can capture waveforms in files, viewable with standard waveform viewer tools like gtkwave.

Challenges of SystemC:

• Lack of Reflection API: C++ lacks a reflection API, such as those in languages like Python, making runtime error reporting and static analysis more difficult. To mitigate this, SystemC coding sometimes involves annotating structures as strings, and the C preprocessor can help minimize redundant identifier input.
• C++ Expertise Shortfall: Many hardware engineers are not well-versed in C++, and improper use of the library can lead to complex and obscure C++ error messages.

Advantages of SystemC:

• High Performance: Coding in C++ inherently provides exceptional performance.
• Industry Standard: SystemC is an established standard in the Electronic Design Automation (EDA) industry, allowing for modeling and implementation of common behavioral code, including application code and device drivers, in a unified language.

SystemC uses the SC_MODULE and SC_CTOR macros to define components. For example, a binary counter can be defined as an SC_MODULE with a constructor created using SC_CTOR. Behavioral actions triggered on clock edges can be defined using SC_METHOD. A sample code might include a 10-bit binary counter implemented as a SystemC class module.

SystemC provides a powerful framework for hardware modeling and simulation using C++, with templated channels serving as the common interface between components. Derived forms such as sc_in, sc_out, and sc_signal are frequently used. These channels implement the compute/commit paradigm for delta cycles, which helps avoid race conditions in zero-delay models.

SystemC Threads and Methods

SystemC allows modules to have their own threads and stacks. Due to the small memory footprint, it is preferable to operate in a trampoline style that uses non-blocking upcalls only. For efficiency, it’s recommended to use SC_METHOD as often as possible. SC_THREAD should be reserved for situations where maintaining significant state in the program counter is necessary or where asynchronous (active) behavior is required.

SystemC Plotting and GUI

SystemC supports waveform output by dumping signals into Verilog Change Dump (VCD) files, which can be visualized later using tools like gtkwave or ModelSim. VCD files store lists of net names and their value changes, timestamped for accurate visualization.

Enhancing Modeling Efficiency

Using SystemC channels to pass more data per kernel operation can lead to improved modeling efficiency. For instance, defining a capsule structure to transmit two integers simultaneously is a step toward effective transaction modeling.

SystemC is thus a valuable tool for hardware design and modeling, leveraging the robust features of C++ to meet a wide range of modeling and simulation needs. However, it demands a deep understanding of C++ and requires skilled engineering knowledge to be used effectively.